View SPT7853SCT_4571679.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SPT7853
TRIPLE 10-BIT, 30 MSPS A/D CONVERTER
FEATURES
* * * * * * * * Three 10-bit, 30 MSPS ADCs on one chip SINAD of 54.5 dB @ IN = 3.58 MHz Channel-to-channel cross talk: -66 dB typical Channel-to-channel gain matching of <0.1 dB Single 2X sample rate clock Total power dissipation: 580 mW (typical) Tri-state +3 V to +5 V digital outputs CMOS-compatible Single +5 V power supply
APPLICATIONS
* * * * * CCIR-601 (4:2:2/4:4:4) digital component video RGB video decoding Medical imaging Flat panel displays PC projectors
GENERAL DESCRIPTION
The SPT7853 has three 10-bit analog-to-digital converters on one CMOS chip, each with a sample rate of 30 MSPS. This device is ideal for professional-level video decoding to 4:2:2/4:4:4 CCIR-601 standard specifications for component digital video, including YCrCb and RGB decoding, professional video equipment, video frame grabbers, medical imaging, flat panel display and projection applications. The SPT7853 offers significant advantages over discrete single-channel A/D implementations. Board area, package count, system cost and power dissipation can greatly be reduced by using a single SPT7853 device. In addition, several performance advantages exist, including low channel-to-channel cross-talk noise and well matched channelto-channel gain specifications. The three analog-to-digital converters are driven from a common 2X sample rate CMOS clock. The SPT7853 typically consumes only 580 mW of total power from a single +5 V supply. Digital outputs can operate with +3 V or +5 V logic and are tri-state capable. The SPT7853 is offered in a small 52-pin thin quad flat pack (TQFP) package and operates over the 0 to +70 C commercial temperature range.
BLOCK DIAGRAM
VRH Force/Sense VRL Force/Sense 2 2 Reference Ladder 10 Output Buffer
VINA
T/H
ADCA
DA0-9
VINB
T/H
ADCB
10
Output Buffer
DB0-9
VINC
T/H
ADCC Timing Generation
10
Output Buffer
DC0-9
Clock
DAV Output Enable
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages VDD .................................................................................................... +6 V OVDD ................................................................................................. +6 V Temperature Analog Inputs .................................. -0.5 V to VDD +0.5 V VREF ................................................ -0.5 V to VDD +0.5 V Clock Input ...................................... -0.5 V to VDD +0.5 V
Note:
Output Currents Digital Outputs ....................................................... 10 mA Temperature Operating Temperature ................................ 0 to + 70 C Junction Temperature ......................................... +150 C Lead, Soldering (10 seconds) ............................. +300 C Storage .................................................... -65 to +150 C
1. Operation at any Absolute Maximum Rating is not implied and operation beyond the ratings may cause damage to the device. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=OVDD=+5.0 V, VIN=0 to 4 V, S=30 MSPS, CLK=60 MHz, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS DC Performance Resolution Differential Linearity Integral Linearity Analog Input Input Voltage Range2 Input Resistance Input Capacitance Input Bandwidth (Full Power) -Full-Scale Error2 +Full-Scale Error2 Reference Ladder Resistance Timing Characteristics Conversion Rate Clock Duty Cycle Range Clock-to-Sample Rate Relationship Pipeline Delay (Latency) Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits IN = 3.58 MHz IN = 10.0 MHz Signal-to-Noise Ratio IN = 3.58 MHz IN = 10.0 MHz Total Harmonic Distortion IN = 3.58 MHz IN = 10.0 MHz Signal-to-Noise + Distortion Ratio IN = 3.58 MHz IN = 10.0 MHz
2The
TEST CONDITIONS
TEST LEVEL
MIN
SPT7853 TYP 10 0.5 1.0
MAX
UNITS Bits LSB LSB
s = 20 MSPS s = 20 MSPS
V V IV IV V V V V VI VI IV IV IV V V VRLS
VRHS 50 5 120 0.5 0.25 170
120 30 45
220
V k pF MHz %FS %FS MSPS % Clock Cycles ns ps
55 2:1 12 5 15
@ 25 C @ 0 to 70 C @ 25 C @ 25 C @ 0 to 70 C @ 25 C @ 25 C @ 0 to 70 C @ 25 C @ 25 C @ 0 to 70 C @ 25 C
VI V V VI V V VI V V VI V V
8.3
8.7 8.0 7.4 56 51.6 48 -58 -54.6 -51 54.5 49.7 46
Bits Bits Bits dB dB dB dB dB dB dB dB dB
53
-56
52
full-scale range spans the reference ladder sense pins, VRHS and VRLS. Refer to the Voltage Reference section for discussion.
SPT7853
2
12/14/99
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=OVDD=+5.0 V, VIN=0 to 4 V, S=30 MSPS, CLK=60 MHz, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. TEST CONDITIONS TEST LEVEL SPT7853 TYP
PARAMETERS Dynamic Performance Spurious Free Dynamic Range IN = 3.58 MHz Channel-to-Channel Cross Talk IN = 3.58 MHz Channel-to-Channel Gain Matching Differential Phase Differential Gain Power Supply Requirements VDD Supply Voltage OVDD Supply Voltage Supply Current IDD OIDD Power Dissipation Without reference ladder Including reference ladder Digital Inputs/Outputs Digital Input Logic 1 Voltage Digital Input Logic 0 Voltage Digital Output Logic 1 Voltage Digital Output Logic 0 Voltage tRISE/tFALL (CL = 10 pF) OEN to Data Output
MIN
MAX
UNITS
@ 25 C @ 0 to 70 C
V V V V V V IV IV VI V +4.75 +2.7
65 56.3 -66 0.1 0.5 0.5 +5.0 +5.25 +5.25 105 11
dBc dBc dB dB Degree % V V mA mA mW mW V V V V ns ns
81 9 485 580 4.0
CL = 10 pF CL = 10 pF
V VI VI VI VI VI V V
750
IOH = 500 A IOL = 800 A
1.0 OVDD -0.5 0.4 10 12
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
SPT7853
3
12/14/99
Figure 1a - Timing Diagram 1
1
ANALOG IN CLOCK IN SAMPLING CLOCK (Internal)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
INVALID
VALID
DIGITAL OUT
1
2
3
4
5
6
7
8
9
10
11
DATA VALID
Figure 1b - Timing Diagram 2
tC tCH tCLK CLOCK IN tOD DATA OUTPUT DA, DB, DC Data 0 Data 1 Data 2 tCL
DATA VALID tS
tDAV
tDAV
Table I - Timing Parameters
Description Conversion time Clock period Clock duty cycle Clock to output delay (15 pF load) tOD DAV pulse width Clock to DAV tDAV tD Parameters tC tCLK Min 2 x tCLK 16.67 45 50 19 tCLK 6.5 55 Typ Max Units nS nS % nS nS nS
SPT7853
4
12/14/99
TYPICAL PERFORMANCE CHARACTERISTICS
THD, SNR, SINAD vs Input Frequency
65
80
THD, SNR, SINAD vs Sample Rate
IN=3.58 MHz
70
THD
60
THD, SNR, SINAD (dB)
THD, SNR, SINAD (dB)
THD
60
55
SNR SINAD
50
SNR
50
SINAD
45
40
40
30
35 0 2 4 6 8 10
20 0 10 20 30 40
Input Frequency (MHz)
Sample Rate (MSPS)
THD, SNR, SFDR, SINAD vs Temperature
70
600
Power Dissipation vs Sample Rate1
THD, SNR, SFDR, SINAD (dB)
SFDR
Power Dissipation (mW)
65
500
60
400
THD SNR
55
300
SINAD
50
200
100
45
0
40 0 20 40 60 80
0
5
10
15
20
25
30
35
40
Sample Rate (MSPS)
Note 1: Power dissipation does not include reference.
Temperature (C)
Spectral Response
0
Large Signal Bandwidth
1.0
CLK 30 MHz IN=3.58 MHz
0.5 0
-20
Amplitude (dB)
-40
-0.5
-60
-80
-100
-120 0 5 10
dB
-1.0 -1.5 -2.0 -2.5 -3.0
Frequency (MHz)
15 x106
0
25
50
75
100
125
Frequency (MHz)
SPT7853
5
12/14/99
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the stated device performance. Figure 2 shows the typical interface requirements when using the SPT7853 in normal circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. Figure 2 - Typical Interface Circuit
AGND
Ferrite Bead
The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each SAR ADC uses 16 clock cycles to complete a conversion. The clock cycles are allocated as follows: Table II - Clock Cycles
Clock 1 2 Operation Reference zero sampling Auto-zero comparison Auto-calibrate comparison Input sample 11-bit SAR conversion Data transfer
DGND
3 4
Hi-Z +D2.7V-5V
OEN REF IN (+4V typ)
4.7 +
5-15 16
VRHF VRHS VRLF VRLS VRLT VCAL DA0-9 DB0-9 10
Enable
SPT7853
DC0-9 DAV OVDD
10
VIN1 VIN2 VIN3
VINA VINB VINC
+D2.7V-5V DGND
DGND
AGND
VDD
CLK
Clock Input
Interfacing Logic
10
The 16-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by two clock cycles so that the analog input is sampled on every other cycle of the input clock by exactly one ADC section. After 16 clock periods, the timing cycle repeats. The sample rate for the configuration is one-half of the clock rate, e.g., for a 60 MHz clock rate, the input sample rate is 30 MHz. The latency from analog input sample to the corresponding digital output is 12 clock cycles. * Since only eight comparators are used, a huge power savings is realized.
+ 4.7 AGND NOTES: 1. 2. 3. 4. Place the Ferrite bead as close to the ADC as possible. All capacitors are 0.01 microfarad surface mount unless otherwise specified. Place 0.01 microfarad surface mount as close to the respective decoupling pin as possible. All input pins (references, analog inputs, clock input and /OEN) must be protected to within the specified absolute maximum ratings. +A5
* The auto-zero operation is done using a closed loop system that uses multiple samples of the comparator's response to a reference zero. * The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each ADC section. * Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. * The total input capacitance is very low since sections of the converter which are not sampling the signal are isolated from the input by transmission gates.
POWER SUPPLIES AND GROUNDING
The digital and the analog supply voltages on the SPT7853 are internally derived from a single analog supply. A separate digital supply must be used for all interface circuitry (OVDD). Connect the digital ground (DGND) to the analog ground plane, as shown in figure 2, to prevent possible latch-up condition.
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in the block diagram. Each ADC uses a parallel SAR architecture. Each contains eight identical successive approximation ADC sections, all operating in parallel, a 16-phase clock generator, an 11-bit 8:1 digital output multiplexer, correction logic, and a voltage reference generator which provides common reference levels for each ADC section.
VOLTAGE REFERENCE
The SPT7853 requires the use of a single external voltage reference for driving the high side of the reference ladder of each ADC. It must be within the range of 3 V to 5 V. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a second reference. The analog input voltage range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS.
SPT7853
6
12/14/99
Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 3, offset and gain errors of less than 2 LSB can be obtained. Figure 3 - Ladder Force/Sense Circuit
+ -
The reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from VRHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS. Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF - VRHS = 7% of (VRHF - VRLF) (typical), and the bottom side voltage drop for VRLS to VRLF will equal: VRLS - VRLF = 8.8% of (VRHF - VRLF) (typical). Figure 4 shows an example of expected voltage drops for a specific case. VREF of 4.0 V is applied to VRHF, and VRLF is tied to AGND. A 280 mV drop is seen at VRHS (= 3.72 V) and a 350 mV increase is seen at VRLS (= 0.35 V).
VRHF
VRHS
VRLS + -
+4.0 V External Reference VRHS (+3.72 V) VRLS (0.35 V)
350 mV
VRLF
ANALOG INPUT
The input voltage range is from VRLS to VRHS and will scale proportionally with respect to the voltage reference. (See voltage reference section.) The drive requirements for the analog inputs are very minimal when compared to most other converters, due to the SPT7853's extremely low input capacitance of only 5 pF and very high input resistance of 50 k. The analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. Figure 5 - Recommended Input Protection Circuit
+V
R
All capacitors are 0.01 F
Figure 4 - Simplified Reference Ladder Drive Circuit without Force/Sense Circuit
280 mV
R/2
R
AVDD
R
R=30 (typ) All capacitors are 0.01 F
D1
R
Buffer
R
47 D2
ADC
R
R/2
VRLF (AGND) (0.0 V)
-V D1 = D2 = Hewlett Packard HP5712 or equivalent
In cases where wider variations in offset and gain can be tolerated, VREF can be tied directly to VRHF and AGND can be tied directly to VRLF as shown in figure 4. Decouple force and sense lines to AGND with a 0.01 F capacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account:
SPT7853
7
12/14/99
CALIBRATION
The SPT7853 uses an auto-calibration scheme to ensure 10-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 10-bit accuracy during device operation. This process is completely transparent to the user. Upon powerup, the SPT7853 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10-bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10k clock cycles are required. This results in a minimum calibration time upon powerup of 150 sec. Once calibrated, the SPT7853 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7853 to remain in calibration.
CLOCK INPUT
The SPT7853 is driven from a single-ended input clock. Because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance. The device's sample rate is 1/2 of the input clock frequency. (See the timing diagram.)
DIGITAL OUTPUTS
The digital outputs for each channel (D0-D9) are driven by a separate supply (OVDD) ranging from +3 V to +5 V. This feature makes it possible to drive the SPT7853's CMOScompatible outputs with the user's logic system supply. The format of the output data (D0-D9) is straight binary. (See table III.) The outputs are latched on the rising edge of CLK. These outputs can be switched into a tri-state mode by bringing OEN high. Table III - Output Data Information
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robustness to 3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition times. Figure 6 - On-Chip Protection Circuit
VDD
120
ANALOG INPUT +F.S. + 1/2 LSB +F.S. -1/2 LSB +1/2 F.S. +1/2 LSB 0.0 V
Analog
OUTPUT CODE D9-D0 11 1111 11 1111 00 0000 00 0000 1111 111O 000O 0000
OO OOOO OOOO
(O indicates the flickering bit between logic 0 and 1).
DATA AVAILABLE
120
Pad
The Data Available pin goes high when the data output bits are valid (see figure 1b). Note: Optimal performance of the data valid pin is achieved when using an input clock with a minimum span range of 1 V (clock low) to 4 V (clock high).
EVALUATION BOARD
The EB7853 Evaluation Board is available to aid designers in demonstrating the full performance of the SPT7853. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note (AN7853) describing the operation of this board as well as information on the testing of the SPT7853 is also available. Contact the factory for price and availability.
POWER SUPPLY SEQUENCING CONSIDERATIONS
All logic inputs should be held low until power to the device has settled to the specific tolerances. Avoid power decoupling networks with large time constants which could delay VDD power to the device.
SPT7853
8
12/14/99
PACKAGE OUTLINE
52-Lead TQFP
A B
52 40
INCHES SYMBOL A MIN MAX 0.472 typ 0.394 typ 0.472 typ 0.394 typ 0.0630 typ 0.0256 typ 0.009 0.013 0.0394 typ 0.004 0.018 0 0.006 0.029 7
MILLIMETERS MIN 12.0 typ 10.0 typ 12.0 typ 10.0 typ 1.60 0.65 typ 0.22 1.0 typ 0.09 0.45 0 0.16 0.75 7 0.33 MAX
1
39
B C D
C
D
E F
13 27
G H
H J I
14
26
I J K
E F G
K
SPT7853
9
12/14/99
PIN ASSIGNMENTS
52 VRHF 51 AGND 43 DA2 42 DA1 40 DGND 48 DA7 44 DA3 50 DA9 47 DA6 49 DA8 46 DA5 45 DA4 41 DA0
PIN FUNCTIONS
Name VINA VINB
39 CLK 38 DB9 37 DB8 36 DB7 35 DB6 34 DB5 33 DB4 32 DB3 31 DB2 30 DB1 29 DB0 28 DAV 27 OVDD
Function Analog input for channel A Analog input for channel B Analog input for channel C
VRHS VRLF VRLS VRLT AGND VINA AGND VINB VDD VCAL AGND VINC AGND
1 2 3 4 5 6 7 8 9 10 11 12 13
VINC
DA0-DA9 CMOS-compatible digital output data for channel A (+2.7 V to +5.0 voltage logic) DB0-DB9 CMOS-compatible digital output data for channel B (+2.7 V to +5.0 voltage logic) DC0-DC9 CMOS-compatible digital output data for channel C (+2.7 V to +5.0 voltage logic) OEN CLK VRHF VRHS VRLF VRLS VDD OVDD AGND DGND VRLT VCAL DAV Output enable pin. (Low = enabled; High = high impedance) CMOS-compatible input clock (2x of sample rate). Input for top of reference ladder (force) Input for top of reference ladder (sense) Input for bottom of reference ladder (force) Input for bottom of reference ladder (sense) Analog +5 V; Digital +5 V Output supply +2.7 / +5 V Analog ground Digital ground Tie to VRLS Calibration reference Data available
DC1 17
DC5 21
DC8 24
DC2 18
DC6 22
DC9 25
N/C 14
OEN 15
DC0 16
ORDERING INFORMATION
PART NUMBER SPT7853SCT TEMPERATURE RANGE 0 to +70 C PACKAGE TYPE 52-Pin TQFP
VDD 26
DC3 19
DC4 20
DC7 23
SPT7853
10
12/14/99

▲Up To Search▲

Price & Availability of SPT7853SCT

	To Download SPT7853SCT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .